Conventionally, an information processing apparatus such as a personal computer may have had a memory module such as a DIMM (Dual Inline Memory Module) which is a main memory. For example, as illustrated in FIG. 1, an information processing apparatus 500 includes a CPU (Central Processing Unit) 510, a memory controller 520, and a DIMM 530.
The CPU 510 is an arithmetic processing apparatus which performs data computing and processing and instructs the memory controller 520 to write/read data to/from the DIMM 530. The memory controller 520 is connected to the DIMM 530 and, in accordance with an instruction from the CPU 510, writes or reads data to or from the DIMM 530. The DIMM 530 has a plurality of DRAMs (dynamic random access memories) 531a to 531d, and the DRAMs 531a to 531d store data.
The memories are physically linearly disposed in accordance with the address spaces in the CPU. In recent years, a CPU has used virtual memory which virtually allocates a memory space protected for each process. Thus, a memory management function such as paging has been used which manages the space of a main storage device by dividing the space into pages having a predetermined size. Another method may be memory segmentation. Such a memory management function may be built in a CPU for a personal computer.
The virtual memory refers to a type of memory management method which allows a multitask operating system having discontinuous memory areas to pretend to have continuous memory areas against software (such as processes). The virtual memory provides a system for virtually implementing a larger storage area than a main storage device provided on a computer. The system of the virtual memory allows the use of a part of the memory space for a large-capacity external storage device such as a hard disk device and may provide the use of a memory space more than the capacity of the memory.
A virtually given address is called a logical address, and a valid address on real memory is called a physical address. The range of logical addresses is called a logical address space, and the range of physical addresses is called a physical address space.
A memory address is a unique identifier of a position on memory to or from which a CPU or other hardware writes and reads data in a computer. Typically, the memory address is expressed by an integer. In a computer in a byte access mode, an address is used for identifying one byte in memory. For that, data which does not fit to one byte is stored in a plurality of bytes occupying continuous addresses. A memory address is used in both logical memory and physical memory.
If a memory error occurs in the DIMM 530 when the information processing apparatus is being used, the information processing apparatus is stopped once, and the failed DIMM 530 may be replaced, imposing a load on a user. A memory error may be caused by a failed block (failure area) which is disabled to store data among memory blocks (storage areas) in the DRAMs 531a to 531d. 
The failure information on the DRAMs 531a to 531d may be stored collectively in a non-volatile memory 532 provided in the DIMM 530, for example, as illustrated in FIG. 1. The failure information on the DRAMs 531a to 531d may be separately stored in non-volatile memory areas provided within the DRAMs 531a to 531d. 
FIG. 2 illustrates an example of a processing routine when a memory error occurs. As illustrated in FIG. 2, upon powered on, a chip set starts monitoring a failure condition of the DRAMs 531a to 531d (S101). Next, the chip set determines whether a failure of the DRAMs 531a to 531d has been detected or not (S102). If no failure is detected in the DRAMs 531a to 531d (No in S102), the processing moves to S101 where the chip set continuously monitors a failure condition of the DRAMs 531a to 531d. On the other hand, if it is determined that a failure in the DRAMs 531a to 531d has been detected (Yes in S102), the chip set saves the failure information (S103) and then powers off (S104). The processing then ends. If the DIMM 530 determined as having a failure is replaced by a new DIMM 530.
The memory error refers to a state that a failed block which is disabled to store data, that is, a failure region occurs in a memory block of a DRAM or a storage area. If a memory has an error, the module having the memory with the error is removed from the computer system, and the memory is replaced. Then, the memory module is inserted to the computer system again.
In a memory module having an error, the failure position in the memory may be analyzed and identified.
For the memory failure analysis, detecting an error address and error bit in the memory of a memory module is important. However, an error address and an error bit displayed by a CPU refer to a logical address and bit, the logical address may be converted to a physical address for identification of the memory having the error.
A memory controller accesses the position instructed in memory in accordance with an instruction from the CPU. When the conversion specifications for converting the logical address instructed by the CPU to a physical address in a memory controller is not available to a user, it is difficult to correlate the memory error and the error in the system having the memory module.
According to a memory error analysis method in a prior art, each of the memory modules may have been inserted to a testing system to determine the memory having an error within a memory module. Furthermore, because the conversion specifications to a physical address are not available, the error analysis has taken time.
When the analysis is performed by a testing system which is different from the system having used the memory module, a difference may occur in the system environment. The difference may result in a different error determination. For that reason, the error may not be found by the test in some error modes.
Detail examples of memory test coverage failures will be described. Following intermittent and marginal failures may cause a system operational failure though the memories having the failures operate normally when they are normally tested alone: 1) A failure caused when a subject memory is operated under a specific algorithm. 2) A failure caused only when the subject memory is dependent on specific write data. 3) A failure under influence a controller or a power supply system, which is caused only when the subject memory is used in applications for the controller or power supply system. 4) A failure under influence a load condition or a transmission system, which is caused only when the subject memory is used in applications for the load condition or transmission system. 5) A failure caused only when the subject memory is used at a specific timing (asynchronously). 6) A failure caused by significant operation variations of memory cells due to repetitive accesses to the subject memory. These failures may be analyzed only when the subject memory is used in an actual system.
The following is a reference document.
[Patent Document 1] Japanese Laid-open Patent Publication No. 11-102328